Shallow trench isolation (STI) is an integrated circuit feature that prevents electrical current leakage between adjacent semiconductor device components. However, STI structures can cause a compressive stress effect in the silicon in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) channel region is located. This phenomenon is generally known as STI stress effect. STI stress effect can cause drive current variation in MOSFETs or, when excess amounts are present, can result in device leakage or other defects.
The STI stress effect in bulk MOS processes is commonly modeled with a standard BSIM4 SPICE model. SPICE (Simulation Program with Integrated Circuit Emphasis) is a general purpose circuit simulator. The Berkeley Short-Channel IGFET Model (BSIM) is a standard model for MOSFET circuit simulation and technology development. BSIM4, the current version of this model, addresses the MOSFET physical effects into sub-100 nm regime. Unfortunately, this model is not suitable for modeling SOI STI stress effect.
SOI devices are similar to devices formed in bulk silicon in that they both have a source, a drain, and a gate structure. SOI devices, however, are formed in a substrate that has a buried isolation region formed below the device layer. This buried isolation region is typically formed by implanting the silicon substrate with oxygen to create a silicon dioxide region, which is commonly referred to as the Separation by Implantation of Oxygen (SIMOX) process.
The buried isolation region reduces or eliminates many of the parasitic problems common to devices formed in bulk silicon. Although the buried isolation region eliminates the need for implanted wells to isolate device components, isolation structures, such as STI structures, are still necessary between neighboring devices. As a result, SOI devices are also susceptible to STI stress effect.
Some efforts have also been made to model isolation stress effects on SOI devices. In one such effort, the stress effect was approximated using a 1/LOD model, where LOD is the length of the outside diameter (OD) of the active region as defined by the device layout. See Ke-Wei Su, “Modeling Isolation-Induced Mechanical Stress Effect on SOI MOS Devices,” SOI Conference, Sep. 29-Oct. 2, 2003, IEEE International, pp. 80-82. However, this effort did not consider the impact of a body-tie, which can impact the stress of the MOSFET.
Thus, it would be beneficial to have an SOI model for modeling the STI stress effect that takes into consideration a body-tie.